Quartus Prime Lite - Difficulties with simulation

Hi,

I got the similar design logic to work on ModelSim Intel edition and Quartus 17.1 (with latest updates) . Here's the code ;

module plltest (
            Clock,
            Reset,
            Locked,
            CountOut
            );
                        
input             Clock;
input             Reset;
output         Locked;
output         CountOut;
wire  CountOut;
wire         Locked;
reg    Count;
wire         PLL_clock;
pll_1 counter_pll (
            .refclk   (Clock),
            .rst         (~Reset),
            .locked   (Locked),
            .outclk_0(PLL_clock)
            );
always@(posedge PLL_clock or negedge Reset) begin
  if (~Reset) begin
     Count <= 4'b0000;
  end
  else begin
    if(Locked) begin
       Count <= Count + 4'b0001;
    end
    else begin
       Count <= 4'b0000;
     end
  end
end //always
assign CountOut = Count;
endmodule

The PLL locked at the input clock, Locked port went high and the counter output was generated. I've included the QAR file, you could extract it and check it out. The device used is Cyclone 5 GX, so the PLL used is Altera_PLL. I'll be generating one more with the Cyclone10LP device and the ALTPLL function as well.

- Abr