Honored Contributor
Honored ContributorI have tried the PLL with and without the "Enable self-reset on loss lock" check. No difference. I tried adding a pfdena input tied to 1'b1 and !ResetN - no difference.
What seems most strange to me is that the simulation shows the c0 output in the HiZ state. I don't understand what's in that block, but I would not expect it to be HiZ ever. I will submit a support case and see if I can send the testpll folder for you to look at. Service request# 11384121 This is the output I get from modelsim: # Reading C:/intelFPGA_lite/17.1/modelsim_ase/tcl/vsim/pref.tcl# do testpll_run_msim_rtl_verilog.do# if {[file exists rtl_work]} {# vdel -lib rtl_work -all# }# vlib rtl_work# vmap work rtl_work# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016# vmap work rtl_work # Copying C:/intelFPGA_lite/17.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini# Modifying modelsim.ini# # vlog -vlog01compat -work work +incdir+C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/source {C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/source/testpll_20180302.v}# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016# Start time: 10:25:41 on Mar 02,2018# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/source" C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/source/testpll_20180302.v # -- Compiling module testpll# # Top level modules:# testpll# End time: 10:25:41 on Mar 02,2018, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# vlog -vlog01compat -work work +incdir+C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/ALTPLL {C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/ALTPLL/testpll_altpll.v}# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016# Start time: 10:25:41 on Mar 02,2018# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/ALTPLL" C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/ALTPLL/testpll_altpll.v # -- Compiling module testpll_altpll# # Top level modules:# testpll_altpll# End time: 10:25:41 on Mar 02,2018, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# vlog -vlog01compat -work work +incdir+C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/db {C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/db/testpll_altpll_altpll.v}# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016# Start time: 10:25:41 on Mar 02,2018# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/db" C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/db/testpll_altpll_altpll.v # -- Compiling module testpll_altpll_altpll# # Top level modules:# testpll_altpll_altpll# End time: 10:25:41 on Mar 02,2018, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# # vlog -vlog01compat -work work +incdir+C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/simulation/source {C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/simulation/source/TB_1_20180301.v}# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016# Start time: 10:25:41 on Mar 02,2018# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/simulation/source" C:/projects/Imelda/FPGA/Imelda_Altera_10CL006_testpll/simulation/source/TB_1_20180301.v # -- Compiling module TB_1# # Top level modules:# TB_1# End time: 10:25:41 on Mar 02,2018, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc" TB_1# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" TB_1 # Start time: 10:25:41 on Mar 02,2018# Loading work.TB_1# Loading work.testpll# Loading work.testpll_altpll# Loading altera_mf_ver.altpll# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES# Loading altera_mf_ver.pll_iobuf# # add wave *# view structure# .main_pane.structure.interior.cs.body.struct# view signals# .main_pane.objects.interior.cs.body.tree# run -all# 0 << Starting Simulation >> # 5651<< Simulation Complete >> restart -f add wave -position end sim:/TB_1/testpll/testPLL/areset add wave -position end sim:/TB_1/testpll/testPLL/pfdena add wave -position end sim:/TB_1/testpll/testPLL/inclk0 add wave -position end sim:/TB_1/testpll/testPLL/locked add wave -position end sim:/TB_1/testpll/testPLL/c0 run -all# 0 << Starting Simulation >> # 5651<< Simulation Complete >> https://alteraforum.com/forum/attachment.php?attachmentid=14913&stc=1 Hopefully this is something simple I've overlooked. If so, I'll be sure to post exactly what it is for others to learn from.
