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Deepak25's avatar
Deepak25
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4 years ago

Quartus Implementation issue

Hi, I’m currently using Synplify FPGA flow to synthesis a design coded in RTL and pass the resulting netlist to Quartus to perform place and route, timing analysis and bitstream generation. S...
Deepak25's avatar
Deepak25
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4 years ago

Looks like we have found a workaround to the register duplication issue. In RTL I can insert synthesis commands to limit the max fanout on the registers that have fanout issues:
reg [31:0] p_ep5_base_d /* synthesis syn_maxfan=2 */;

The number of additional registers that are inserted is minimal and there is little or no impact on utilization