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Deepak25's avatar
Deepak25
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4 years ago

Quartus Implementation issue

Hi, I’m currently using Synplify FPGA flow to synthesis a design coded in RTL and pass the resulting netlist to Quartus to perform place and route, timing analysis and bitstream generation. S...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

Is this a very large design that is failing because the chip is full? Did you enable the aggressive routing option as mentioned in the messages?