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Niko3
Occasional Contributor
Occasional ContributorQuartus II simulation: missing max3000a_ver and output pin stuck at ground
Hi, I am a beginner with Quartus. I use Quartus II 13.0sp1 because I want to use a chip from MAX3000A family. Later versions don't support MAX3000A. To start with a simple design I tested the follo...
FvM
Super Contributor
Super ContributorHello,
you don't consider that Quartus synthesis performs logic minimization. Respectively your asynchronous pulse generation logic is discarded during synthesis. Read Quartus software manual about syn_keep attribute. Applying the attribute to intermediate logic nodes should synthesize the logic as intended. Not sure if the delay is sufficient to generate a stable output pulse, but something of this kind should work.
you don't consider that Quartus synthesis performs logic minimization. Respectively your asynchronous pulse generation logic is discarded during synthesis. Read Quartus software manual about syn_keep attribute. Applying the attribute to intermediate logic nodes should synthesize the logic as intended. Not sure if the delay is sufficient to generate a stable output pulse, but something of this kind should work.
Niko3Thank you, I will check it.
