Quartus II simulation: missing max3000a_ver and output pin stuck at ground

Hello,
you don't consider that Quartus synthesis performs logic minimization. Respectively your asynchronous pulse generation logic is discarded during synthesis. Read Quartus software manual about syn_keep attribute. Applying the attribute to intermediate logic nodes should synthesize the logic as intended. Not sure if the delay is sufficient to generate a stable output pulse, but something of this kind should work.