New Contributor
New Contributor"I don't know if this is related. I observed in the chip planner that all the logic layout is concentrated in the bottom left corner, leaving many resources unused, yet my pins are distributed on three sides. Congestion occurs even when there are still many resources remaining."
The image below is a report of routing utilization.
The blue areas in the image below represent the pins I have actually allocated.
New ContributorI found that changing the initial placement seed seems to solve the problem. However, I still want to know how to avoid this issue by modifying the code?
Super ContributorWhat device is this and what speed are you trying to run at? Do you have a .sdc and are you meeting all timing requirements?
New ContributorThank you for your reply.
I am using the Cyclone V 5CGXFC5C6F23C6. The code for the SDC file is in the attached file.Although I named it as a 500M clock, I actually reduced the frequency to 400M in practice. This can be seen in the SDC file.
By changing the seed to a specific value, after the compilation passes, there are timing violations.
The setup time violation is about 0.6ns.
