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I guess my greatest difficulty is trying to "sync" each 20ms cycle.
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You probably need to add edge detection.
With your faster (50MHz?) clock, do something like below, or maybe adding a synchronizer chain.
reg pwm_prev; // previous sample
wire pwm_rising_edge;
wire pwm_falling_edge;
always @(posedge clk)
begin
pwm_prev <= pwm; // store the current pwm value and save it for later (until next clock)
end
assign pwm_rising_edge = pwm & ~pwm_prev;
assign pwm_falling_edge = ~pwm & pwm_prev;
Then alter your existing counter management to do something like compute your percent value and reset the counters when ' pwm_falling_edge == 1'b1 '
Small comment about your code:
ratio <= ((signalon-10'd50000)/5000);
At some point you are going to want to think of some clever way to avoid doing math like this that uses up FPGA resources, but for now you probably have other things to figure out.
Honored Contributor
