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NShin3's avatar
NShin3
Icon for New Contributor rankNew Contributor
6 years ago

Qsys/Platform Designer does not generate submodule files when using two Avalon MM Slaves

I have created custom Avalon MM slaves. I want to connect them to a Master. The Qsys/Platform Designer tool does not generate submodule files when more than one Avalon slaves are connected to Avalon...
NShin3's avatar
NShin3
Icon for New Contributor rankNew Contributor
6 years ago

Warning: Translator master_0_avalon_master_translator failed to match interface master_0.avalon_master

-- I tried going through the component editor again and recreating the _hw.tcl files and saving and regenerating the system.

Still same warning same problem.

-- For attenuator component which has no effect of address, if i dont use address then how master will identify it ? there should bre address/ location to differentiate with other slave, right ?

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

With only a single addressable location, you don't need the address signal in the component. You'd still give a unique address in Platform Designer when building a system which would then handle which of multiple slaves to access in the interconnect.