New Contributor
Super ContributorVery strange. Do you only have this issue when you connect two or more of the same component to the master? If you connect this custom component and some other component to the same master, does it generate OK?
I would try deleting the custom component's _hw.tcl file, and then go through the Component Editor again. It doesn't make sense that one instance works but more than one doesn't.
Also, maybe you could post the Avalon interface part of the code for the custom component. Maybe there's an issue with how you've set up the Avalon signaling. It might also be useful to see how you've configured the Signals & Interfaces tab of the Component Editor.
#iwork4intel
New ContributorHi,
Thanks for the suggestion.
I have attached Avalon MM master and two slave Verilog files.
Slave : read only, with signals and interfaces
New ContributorThis is master signals and interface tab with code.
Conduit signals are for Controlling master through FPGA switches.
New Contributorslave signals and interfaces, with code.
This slave is for write operation only.
