Forum Discussion
Hi,
Quartus/Platform designer/Qsys tool will generate all the required files.
- include the .v/.vhd file of your Custom component (Project navigator->files-?add/remove files in the project)
- Quartus will update only the required files after changes which also saves the generation or compilation time. However, you can delete the folder/file and regenerate.
Regards
Anand
- NShin36 years ago
New Contributor
Hello Anand,
I followed this process but still have the same problem.
Image 1 : Single Avalon MM slave.
-- Submodules folder generated with all sub files.
-- inst file is also generated.
Image 2 : Two Avalon MM slaves.
-- No Submodules folder generated.
-- No inst file.
-- Only QIP file.
Thanks and Regards,
Niranjan
- AnandRaj_S_Intel6 years ago
Regular Contributor
Hi,
May be due to custom component.
follow the steps from below file.
Can you share the project?
Regards
Anand
- NShin36 years ago
New Contributor
Hi,
I followed this same document to create custom components.
Only difference is I am using conduit signals to get data from FPGA modules instead of instantiating inside slave MM interface.
I have shared verilog files of master and slaves in the comments below.
Thanks and regards,
Niranjan