Qsys module with JTAG Avalon Master and Slave

I have created a Qsys system that consists of a JTAG to Avalon Master Bridge (Master) and an Avalon Memory Mapped Slave. The slave is created using a .vhd file which has the following ports:

csi_clockreset_clk : in std_logic;

csi_clockreset_reset_n : in std_logic;

avs_qsys_read : in std_logic;

avs_qsys_readdata : out std_logic_vector(15 downto 0);

avs_qsys_write : in std_logic;

avs_qsys_writedata : in std_logic_vector(15 downto 0);

avs_qsys_address : in std_logic_vector(15 downto 0);

coe_writedata_ext : out std_logic_vector(15 downto 0);

coe_write_ext : out std_logic;

coe_read_ext : out std_logic;

coe_address_ext : out std_logic_vector(15 downto 0);

coe_reset_ext : out std_logic;

coe_clk_ext : out std_logic;

coe_readdata_ext : in std_logic_vector(15 downto 0)

And, I perform the following assignments:

coe_writedata_ext <= avs_qsys_writedata;

coe_write_ext <= avs_qsys_write;

coe_read_ext <= avs_qsys_read;

coe_address_ext <= avs_qsys_address;

coe_reset_ext <= csi_clockreset_reset_n;

coe_clk_ext <= csi_clockreset_clk;

avs_qsys_readdata <= coe_readdata_ext;

The address map for the Qsys is 0x00000000 to 0x0001FFFF. Now, I used this Qsys system and an external RAM (megawizard function) to perform reads and writes to the memory. I am using System Console, in Qsys, to run a TCL script to perform reads and writes using the following commands:

master_write_16 and master_read_16

I have also added a signaltap file to the project to monitor changes in the signal values. Now, in the System Console window in order to read and write to address 0x0000, I used the following commands:

1. master_write_16 $jtag_master 0x0000 0x1

2. master_read_16 $jtag_master 0x0000 1

After each command I check the values shown by signaltap. For all the address entries, the data written and read for the memory is consistent. But, the address shown by signal tap (coe_address_ext) is not the same as the address I accessed using the TCL command.

For example, when I type the following commands in the System Console window, the following signaltap values for the address appear-

tcl command ----------------------------coe_address_ext (shown by signaltap)

master_write_16 $jtag_master 0x0000 0x1 -------------------0x0000

master_write_16 $jtag_master 0x0002 0x3 -------------------0x0000

master_write_16 $jtag_master 0x0004 0x5 -------------------0x0002

master_write_16 $jtag_master 0x0006 0x7 -------------------0x0002

master_read_16 $jtag_master 0x0000 1 ---------------------- 0x0002

master_read_16 $jtag_master 0x0002 1 ---------------------- 0x0002

master_read_16 $jtag_master 0x0004 1 ----------------------0x0004

master_read_16 $jtag_master 0x0006 1 ----------------------0x0004

I do not understand as to why is the address value captured by signaltap different then what I am entering using tcl command. Is there some kind of address mapping?

I will appreciate if someone can help me with the issue. Thanks.