QSYS, minor glitches with parameterized ports

If possible I recommend opening a service request and attaching your component so that the tools will be fixed: http://www.altera.com/mysupport -1 is used as a default for a parameter which will get filled in later.

By the sounds of it the default value is not being filled in correctly. I'm guessing if you add an elaboration callback to the .tcl file you can work around this bug. If you want to see an example take a look at the .tcl files for the read and write masters in this design: http://www.alterawiki.com/wiki/modular_sgdma (verilog based but the .tcl commands will be the same)