Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorQsys generation failed using DDR3 SDRAM controller with uniPHY - Cyclone V GX
Hello, i have an Altera Cyclone V GX with Quartus 13.0 (Windows 7 Web Edition) and i implemented a Qsys system using a DDR3 SDRAM controller with uniPHY. When i try to generate, the following erro...
Altera_ForumHonored Contributor
Honored ContributorHi,
I've created several DDR3 UniPHY designs with various Quartus versions and have not see the error messages you're seeing; although I was using the Subscription Edition of Quartus. This thread http://www.alteraforum.com/forum/showthread.php?t=43992 contains a DDR3 UniPHY design for the BeMicro-CV (Cyclone V) board (see the zip file with post# 5). The readme.txt in the DDR design folder contains the steps used to create the IP core. Perhaps you could read that to see if you've configured the core differently, or whether the problem is that you are using the Web Edition. Cheers, Dave
