Qsys generation failed using DDR3 SDRAM controller with uniPHY - Cyclone V GX

Hello, i have an Altera Cyclone V GX with Quartus 13.0 (Windows 7 Web Edition) and i implemented a Qsys system using a DDR3 SDRAM controller with uniPHY.

When i try to generate, the following errors occur:

Error: s0: Error during execution of "{C:/altera/13.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally

Error: s0: Execution of command "{C:/altera/13.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed

Error: s0: ]2;Altera Nios II EDS 13.0 [gcc4]C:/altera/13.0/quartus/bin/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../strIV_cycV(4)_altmemddr_0_s0_AC_ROM.hex -inst_rom ../strIV_cycV(4)_altmemddr_0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_MR0=0010000110001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0010100110000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000001000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0010001001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0010011001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000010000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0

Error: s0: child process exited abnormally

Error: s0: Cannot find sequencer/sequencer.elf

Error: s0: An error occurred

while executing

"error "An error occurred""

(procedure "_error" line 8)

invoked from within

"_error "Cannot find $seq_file""

("if" then script line 2)

invoked from within

"if {[file exists $seq_file] == 0} {

_error "Cannot find $seq_file"

}"

(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)

invoked from within

"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""

invoked from within

"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"

("if" then script line 2)

invoked from within

"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {

set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."

(procedure "generate_qsys_sequencer_sw" line 746)

invoked from within

"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."

invoked from within

"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."

("if" else script line 2)

invoked from within

"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {

set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."

(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 195)

invoked from within

"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"

invoked from within

"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"

(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)

invoked from within

"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"

invoked from within

"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {

set file_name [file tail $genera..."

(procedure "generate_synth" line 8)

invoked from within

"generate_synth strIV_cycV(4)_altmemddr_0_s0"

Info: s0: "altmemddr_0" instantiated altera_mem_if_ddr3_qseq "s0"

Error: Generation stopped, 6 or more modules remaining

Info: strIV_cycV(4): Done strIV_cycV(4)" with 59 modules, 280 files, 6195125 bytes

Error: ip-generate failed with exit code 1: 7 Errors, 0 Warnings

I tried to fix this errors several times but i always failed. I tried to change some DDR3 SDRAM controller with uniPHY core parameters but during the generation i obtained the same errors.

I think the trouble concerns the sequencer of the uniPHY. How can i manage the sequencer? Where i can find sequencer.elf?

How can i fix this errors? :confused:

Thanks.

Luca