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Altera_Forum's avatar
Altera_Forum
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14 years ago

QSYS and JTAG Debugger

I have a design I've built in QSYS using a 16-bit bus. I'd like to include the JTAG to Avalon Master in my design so that I can do a quick system-level check using TCL commands before handing it off ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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It was a symbol width mismatch. I had not understood why Altera was asking for the symbol size and had defined the 16-bit bus width parts as having 16-bits per symbol. Now I also understand the addressing increments as well.

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Great! Now you can move onto your next problem :)

Cheers,

Dave