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Altera_Forum
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14 years ago

QSYS and JTAG Debugger

I have a design I've built in QSYS using a 16-bit bus. I'd like to include the JTAG to Avalon Master in my design so that I can do a quick system-level check using TCL commands before handing it off ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

The JTAG-to-Avalon-MM master has a 32-bit data bus. See Chapter 18

http://www.altera.com/literature/ug/ug_embedded_ip.pdf

Under SOPC Builder you do not have any option to change the bus width. I assume that under Qsys its the same.

The Qsys system builder should insert width adapters.

If it does not, just create your own components with 32-bit widths, and generate two 16-bit transactions if all byte-enables are enabled. This is what I do to make 16-bit SRAM look like 32-bit SRAM.

Cheers,

Dave