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Altera_Forum
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12 years ago

Qsys : Arria V: PCIe Avalon ST source to SGDMA Avalon ST sink interconnect error

Hi

I have configured a PCIe Hard IP for X4 Gen 2 hard macro with Avalon streaming interface. This necessitates a Avalon ST - 128 bit application interface.

In trying to connect the Avalon ST tx, to the Avalon ST input on an SGDMA configured for "stream to memory", I continue to get

the error

connecting a 128 bit source to an 8 bit sink

My understanding for the SGDMA is that the symbol is 8 bits so I configured the data width to 16 (in the assumption that this

corresponds to 16*8 = 128 bits)

Is my understanding incorrect?

Thanks

Fionbarra

Additional information

I am using 64 bit version of Quartus 13.1 software.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Is there anyone out there that can help me on this as I am quite stuck?

    I have even tried using bus width adapters but to no avail.

    Fionbarra
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I've never used the PCIe hard IP, so I can only guess here, but in order for this to work you will need to define the stream interface from the PCIe component as 8-bit symbols with 16 symbols pet beat. The SGDMA on the other end, is always configured as 8-bit symbols and either 1,2, 4 or 8 symbols per beat, depending on the data width that you selected. With this kind of configuration, a simple bus width adapter IP between the two components should fix the problem. In SOPC builder you must add it manually (Avalon-ST Data Format adapter) and in theory this is automatic in QSys but I've never tested it.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thanks for the help Daixiwen

    but I am still having issues here.

    1) The symbol width is not configurable in the PCIe hard macro template in Qsys (at least I have not located any window to paramaterize the symbol width in the PCIe hard macro template).

    3) I have instantiated the Avalon ST Data Format adapters in the design BUT they assume that the symbol widths are "common" for the inputs and outputs i.e. if the output/input symbol width is 8 bits then the input/output symbol width is assumed to eb 8 bits also.

    Which leaves me with a bit of a predicament as

    The error text that I am getting is

    " Error: System.pcie_cv_hip_ast_0.rx_st/data_format_adapter_0.in: The source has 128 bits per symbol, while the sink has 8"

    Which implies to me that the input symbol width should be configured as 128 bits BUT obviously this is in conflict with the 8 bit symbol width of the SGDMA controller.

    Fionbarra
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    As I said I never used that IP, so I can only offer generic help. Is there an example design somewhere that connects the PCIe IP to a DMA? You could see how it's done and reproduce it in your project.

    Other than that, the only way I can think of is to make a custom stream component that just connects a sink to a source, but defined as 128-bit symbols on one side and 8-bit symbols on the other. You can connect all the signals one to one, except that the 8-bit side will also need an "empty" signal, 6-bits wide. For the 8-bit sink you can just ignore the empty signal, and for a 8-bit source, set it to all zeroes. Then of course make sure that all your DMA transfers always transfer a number of bytes multiple of 16.