Qsys : Arria V: PCIe Avalon ST source to SGDMA Avalon ST sink interconnect error

I've never used the PCIe hard IP, so I can only guess here, but in order for this to work you will need to define the stream interface from the PCIe component as 8-bit symbols with 16 symbols pet beat. The SGDMA on the other end, is always configured as 8-bit symbols and either 1,2, 4 or 8 symbols per beat, depending on the data width that you selected. With this kind of configuration, a simple bus width adapter IP between the two components should fix the problem. In SOPC builder you must add it manually (Avalon-ST Data Format adapter) and in theory this is automatic in QSys but I've never tested it.