Qsys : Arria V: PCIe Avalon ST source to SGDMA Avalon ST sink interconnect error

Thanks for the help Daixiwen

but I am still having issues here.

1) The symbol width is not configurable in the PCIe hard macro template in Qsys (at least I have not located any window to paramaterize the symbol width in the PCIe hard macro template).

3) I have instantiated the Avalon ST Data Format adapters in the design BUT they assume that the symbol widths are "common" for the inputs and outputs i.e. if the output/input symbol width is 8 bits then the input/output symbol width is assumed to eb 8 bits also.

Which leaves me with a bit of a predicament as

The error text that I am getting is

" Error: System.pcie_cv_hip_ast_0.rx_st/data_format_adapter_0.in: The source has 128 bits per symbol, while the sink has 8"

Which implies to me that the input symbol width should be configured as 128 bits BUT obviously this is in conflict with the 8 bit symbol width of the SGDMA controller.

Fionbarra