Qsys - Nios write to FIFO

Hello,

In my design project, Nios needs to write to an external FIFO. I created a custom Avalon MM component for the purpose. When Nios write to the custom component, the design expects to see the signals at the output of the Nios core.

https://www.alteraforum.com/forum/attachment.php?attachmentid=7813

Listed below is the VHDL code of the said custom Nios-FIFO interface:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY out_fifo_avalon_interface IS

PORT (

clock, resetn : IN STD_LOGIC;

write, chipselect : IN STD_LOGIC;

writedata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

out_fifo_clk_export, out_fifo_cs_export : out STD_LOGIC;

Q_export : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END out_fifo_avalon_interface;

ARCHITECTURE Structure OF out_fifo_avalon_interface IS

BEGIN

out_fifo_clk_export <= clock;

out_fifo_cs_export <= chipselect;

Q_export <= writedata;

END Structure;

The project compiled ok (no hard errors). However, when Nios write to FIFO interface MM address, chipselect and clock are nowhere to be seen on the scope.

Could someone help? Thanks.