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Honored Contributor
Honored ContributorQsys - Nios write to FIFO
Hello, In my design project, Nios needs to write to an external FIFO. I created a custom Avalon MM component for the purpose. When Nios write to the custom component, the design expects to see the...
Altera_ForumHonored Contributor
Honored ContributorIts possible that Eclipse was trying to compile your project with an old version of the BSP that didn't have this component, and as a result didn't replace OUT_FIFO_AVALON_INTERFACE_0_BASE with the correct value. I don't use Eclipse that much so I don't know how smart it is when you partially recompile a project.
As for your other line, it looks like you found the solution yourself ;). You should always bypass the cache when accessing a component, either by using the IORD/IOWR macros, or change the address pointer. For the latter you can either set bit 31, as you did, or use the alt_remap_uncached() function provided by Altera, which is a more portable solution.
