New Contributor
Regular ContributorHi,
The models are based on the I/O standard that the user choose and type of termination applied to the signal. Please refer the datasheet for the supported I/O standards and documents related to External Memory Interfaces. Following is the documentation page:
https://www.intel.in/content/www/in/en/products/details/fpga/agilex/7/docs.html
Regards
New ContributorHi,
I was looking through the doc, but I cannot locate the section which mentioned about the driver.
Can share with me the doc name and which sections ?
