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Honored Contributor
Honored ContributorQ: how to combine a Project with its modules into One file to use in another Project
Hi. I would like to combine or package a project I created and tested (in verilog) so I can use it like an IP or as a single module in another project. For example: my top level module has other mo...
Altera_ForumHonored Contributor
Honored ContributorNo need for subscription edition.
Just include the same file by using relative paths, (it's better than absolute, but not a hard requirement) Make the file parameterizeble via parameters (verilog) or generics (VHDL) And that is it.
