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Altera_Forum
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8 years ago

pulse alignment implementation

I have a periodic external pulse signal. My FPGA generates a pulse signal with the same frequency by a state machine. I want to align the phases of the two pulses. I managed to achieve perfect alignm...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Depends on the external signal frequency and frequency range. There are many ways to implement a digital PLL in the FPGA. For fast signal PLL dynamic fast shift is a possible option.