pull up/down resistors

Whilst the FPGA is being configured the pins are tri-stated. Any internal pull-up resistors you might have enabled, won't actually be active until configuration is complete. So during configuration unless another device pulls the signals one way or another, the signals connecting your FPGA to other devices will be floating.

Whether or not you need pull ups/downs on those signals depends on how the other devices will behave with floating inputs - if you need to guarantee that their pins are held in a certain state then you will need pull-ups/downs.

There's no simple answer other than looking at the details of your design. As an example though:

Say you have multiple devices hanging off a bus - i.e. different devices can drive the same signals. Each device has an enable signal from the FPGA to prevent this conflict. While the FPGA is configuring itself you will need to pull up/down these enable lines to stop the devices fighting each other and causing damage.

Hope this helps.

It depends on your application. The larger the pullup resistor value is, the slower the rising and falling edges are. If the you think that you need pull-up or pull down resistors to set outputs to hight or low logical level for safety during power-up because I/O pins remain tri-stated during power-up, I think that you have to.

Anyway, in Quartus-II, you can use the assignment editor to set output to weak pull-up.

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Whilst the FPGA is being configured the pins are tri-stated. Any internal pull-up resistors you might have enabled, won't actually be active until configuration is complete. So during configuration unless another device pulls the signals one way or another, the signals connecting your FPGA to other devices will be floating.

Whether or not you need pull ups/downs on those signals depends on how the other devices will behave with floating inputs - if you need to guarantee that their pins are held in a certain state then you will need pull-ups/downs.

There's no simple answer other than looking at the details of your design. As an example though:

Say you have multiple devices hanging off a bus - i.e. different devices can drive the same signals. Each device has an enable signal from the FPGA to prevent this conflict. While the FPGA is configuring itself you will need to pull up/down these enable lines to stop the devices fighting each other and causing damage.

Hope this helps.

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AFAIK Altera devices have built-in weak pullups at all times (20K-100K or something like that) - so external pullups aren't necessary during configuration.