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Altera_Forum's avatar
Altera_Forum
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11 years ago

PTP 1588 on Cyclone V

Hi

I would like to implement PTP 1588 on my cyclone V EVAL kit DK-DEV-5CEA7N.

My problem is, I don't find any example how to connect all the ports of the TSE-MAC in the QSYS...

Does anyone have some advice how to start de development of ma project?

With the example board update portal I was able to communicate over the simple socket server via telnet to my FPGA. This

could be a good starting point for my project. But as I mentioned I don't know how to connect the PTP 1588 TSE in QSYS...

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi,

    I have the same problem on my cyclone V GX FPGA dev. kit.

    Im sending UDP/PTP sync message (with UDP stack on niosII) but TSE Mac does not put timestamp in PTP packet. (wireshark packet pic. attached). I think my problem is with hardware design (.qsys attached).

    Altera documentation for PTP on cyclone V is deficient..
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I agree that the documentation isn't very good. But it is not the Mac that will put the timestamp information into the PTP packet. All that it does is to give a timestamp for the packet send or receive operation. It is the software responsibility to get that timestamp from the MAC and convert it to the correct PTP time and insert it in the PTP packets.

    I wished too that they provided a design example. As the MAC they use is a Synopsys Designware IP, it may be possible to find examples from other sources on the net.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I saw Cyclone V and incorrectly assumed that it was the Soc Ethernet mac that was used. The Soc Mac supports hardware timestamping but not timestamp insertion in the packet (which are two different things).

    I've never used the TSE in that configuration but according to the documentation it will only insert the timestamp in the sync packets in the 1-step synchronization mode, if the 2-step flag in the flagField of the Ptp frame is 0. Is this our case? The forum reduced the size of your snapshot and it's difficult to see your packet contents.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    tnx for replaying.

    My PTP_TWO_STEP flag is 0. (see picture or wireshark file in attachment)

    https://ibb.co/co7wwf

    I think my problem is with Ethernet Packet Classifier. He should recognize ptp package and message in it. If the (message == ptp sync message) then must send timestamp request to the Mac TSE.

    In my case Packet Classifier does not recognize packet as ptp packet and thats the problem.

    See the picture of my Signaltap, my trigger is set on etherrype_valid.

    https://ibb.co/bn8jrf
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    You are sending your packets as UDP so if I understand the design correctly the ethertype signal that should have been asserted is ethertype.TYPE_UDP_IPV4 and not ethertype.TYPE_NON_PTP.

    It is rather odd that it doesn't even recognize the packet as ptp. Do you need a special configuration for that? I only had a quick look at the user guide and I didn't find anything. I know the MAC from the Cyclone V Soc has a specific configuration bit to enable PTP detection over UDP/Ipv4.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Yes, you understand it correctly.

    No need for special configuration.

    I also tried send PTP over IEEE 802.3. (ethertype.TYPE_PTP in packet classifier), but same result. He recognizet it like ethertype.TYPE_NON_PTP.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I have been looking all over for a full PTP reference design for either Cyclone V SoC or Arria 10 SoC. I see the OP was looking for one as well (albeit for Nios), I wonder if anyone has ever found one? There is the Altera reference design for 1588 which uses Arria V SoC (which is a really expensive device), and when attempting to port that to either Cyclone V or Arria 10, many of the IP blocks are incompatible and the system needs rebuilt, and Linux drivers will not work. I would prefer to run PTP on the dual ARM(SoC), but if there is a good working Nios design, that may be fine as well. I downloaded the zip file attached by nikorenic but it was in 12.0 and I'm using 16.1 so I had errors trying to pull it up...

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    @lemonoje

    There is no PTP reference design for Cylclone. Im using modified "board_update_portal" design. I made some small modifications (TSE Mac, External FIFO, TOD, Packet Classifier). Original BUP design is made in Quartus 12.0, for modification i used 15.1.

    Wich error you had ? Put the error log screen.

    Also i found a cause for ethertype.TYPE_NON_PTP. The problem is in Ethernet header offset 

    /* define Ethernet header size and offset */
# define ETHHDR_SIZE	 (16)
# define ETHHDR_BIAS  (2)

    Now i get ethertype.TYPE_UDP_IPV4 and msg_valid. But egress_timestamp_request_out_valid is still low. (im sending sync message)
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    @lemonoje

    There is no PTP reference design for Cylclone. Im using modified "board_update_portal" design. I made some small modifications (TSE Mac, External FIFO, TOD, Packet Classifier). Original BUP design is made in Quartus 12.0, for modification i used 15.1.

    Wich error you had ? Put the error log screen.

    --- Quote End ---

    Sorry for the long delay, I never saw the reply and I was just checking around and ran across this again. I don't have an error log or anything, I'm just trying to understand how to include LinuxPTP into Linux kernel and filesystem. I also need to know how to set the devicetree bindings (if any). I want to start with any form of PTP (software or HW timestamping) using the SoC HPS EMAC from the ARM-9. After I run make install - can I just copy the output compiled programs to my kernel's filesystem and run the commands? How would I tell the EMAC driver to use the LinuxPTP stack?