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Honored Contributorprogrammable parallel to serial converter
hi can any1 plz help me in vhdl code for programmable parallel to serial converter of 6 to 16 bit.maximum size is 16 bit but dat is nt fixed sometimes we may get 6 bit or 8 bit r etc that should get convert into serial.
I have written code but getting errors plzz check it out make corrections for my code plzzzzzzzz.... library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity P2S is port ( Serial_out : out std_logic; clk : in std_logic; Parallel_data : in std_logic_vector(15 downto 0); DataReady : in std_logic); end P2S; architecture Behavioral of P2S is Signal Shreg : std_logic_vector( 15 downto 0); begin process( clk) variable x : integer := 6; begin if DataReady = '1' then if (clk'event and clk = '1') then x := x+1; for i in 0 to x loop if(parallel_data = i) then Shreg <= parallel_data; else Shreg <= Shreg(0) & Shreg(x downto 1); end if; end loop; end if; else Serial_out <= Shreg(0); End if; End process; End Behavioral; ================================================= ERROR:Xst:1549 - line 51: Range bound must be a constant.6 Replies
Altera_ForumIn this expression x must be a constant:
Shreg(x downto 1); Anyway, your code will not work even if you correct this point. You are writing code as if you were to execute it like a common software language, which HDL is not. Remind that everything you code in HDL must be eventually synthesized by means of logic gates and flip-flops, and they all are supposed to switch on clock edges. Google for parallel to serial converter and you'll find a lot of code samples.- Altera_Forum
ok ok....can you plz help me in writing code for this iam unable to get it. i was trying for this from 1 week but iam unable to get it. plzzzz help me out of this.
Actually for a fixed length iam able to write a program but when coming to programmable parallel to serial iam unable to do dat give me somee tips to write a code for this or else say me how to modify this code....... - Altera_Forum
I try write a draft of code sample.
Please note I wrote it as pseude-code, without any syntax check, so you may (very probable) need to fix some VHDL errors.entity P2S is port ( Serial_out : out std_logic; clk : in std_logic; Parallel_data : in std_logic_vector(15 downto 0); Data_length : in std_logic_vector(3 downto 0); DataReady : in std_logic); end P2S; architecture Behavioral of P2S is signal temp : std_logic_vector(15 downto 0); signal counter: integer; begin process(rst, clk) begin if(clk='1' and clk'event) then if (DataReady) then counter<=0; elsif (counter<Data_length) then Serial_out<=Parallel_data(counter); counter<=counter+1; else Serial_out<='0': end if; end if; end process; end Behavioral; - Altera_Forum
ok thanq.. a small doubt y you have taken data length as 4 bit....
Actually my main aim is that what ever the signal which is of size from 6 to 16 bit wil come then that should get serialized. counter is for calculating the length and then according to the length we r going to serialize ah???? - Altera_Forum
If you have 4bit for data lenght, you can indeed specify values from 1 to 15.
Change it to 5 (or whatever you need) and you can specify length from 1 to 31. - Altera_Forum
ok but in this there is no need of temp signal but y you have taken . If i want to use temp then i can write serial out = temp(0);
Is this right.... And when i simulate any length of data which is from 6 to 16 bit that will get serialized na...... but it is not getting simulated.... how to rectify this plzzzz help me.....
