Forum Discussion
Altera_Forum
Honored Contributor
13 years agoI try write a draft of code sample.
Please note I wrote it as pseude-code, without any syntax check, so you may (very probable) need to fix some VHDL errors.
entity P2S is
port ( Serial_out : out std_logic;
clk : in std_logic;
Parallel_data : in std_logic_vector(15 downto 0);
Data_length : in std_logic_vector(3 downto 0);
DataReady : in std_logic);
end P2S;
architecture Behavioral of P2S is
signal temp : std_logic_vector(15 downto 0);
signal counter: integer;
begin
process(rst, clk)
begin
if(clk='1' and clk'event) then
if (DataReady) then
counter<=0;
elsif (counter<Data_length) then
Serial_out<=Parallel_data(counter);
counter<=counter+1;
else
Serial_out<='0':
end if;
end if;
end process;
end Behavioral;