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Altera_Forum's avatar
Altera_Forum
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18 years ago

Processor not responding

Hi all ,

I developed a custom component(memory mapped). When I integrate it with the NIOS II processor in the sopc builder and try to run the NIOS II embeded systm as hardware I get the error message saying processor fails to respond.

1) when I remove my custom logic the sopc system works fine.

2) When I simulate the system (custom logic + sopc system) as ISS (instruction set simulatro) it passes.

2) my custom component pass in gate-level simulation as well. the custom component has a master interface, slave interface and my logic.

Any suggestion as to where to start the debugging? cos the NIOS II IDE just say the processor fail to respond. How can I figure what make the processor to fail.

shown below is the exact error I am getting. I think my custom component does something for the processor. Because when I remove my custom component from the design everything works fine. How to debug this? any help?

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Does your custom logic in some way interfere with the reset_n pin of the NIOS?

    Or have something to do with the clock frequency?

    This error is too generic, it is very difficult to answer without knowing the design.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    yes I agree, here is some more info about my design , please cut and past it on a new borwser to see the block diagram of the custom logic and sopc system. Please help me to narro down this error. Right now im just trying to integrate one by one. i.e integrate the slave interface first and see if I can write through the slave inter face ... this taking toomuch time ...

    angelfire.com/ga/ganen/system.JPG

    angelfire.com/ga/ganen/SOC.JPG

    http://www.angelfire.com/ga/ganen/system.JPG

    http://www.angelfire.com/ga/ganen/SOC.JPG
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    how to make sure the reset_n is not low?

    adjust reset button on the fpga board? or the verilog code?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You have to check which kind of reset comes from your board (reset 'button'). If this is an active high signal you will have to invert it in your code. If it's an active low signal you will have to check in your code that you don't invert it.