Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Problems with Synthesis ?

Hola All,

I've made some code that describes a counter that first adds one to a count "c", compares its value with an input "N", and if they are the same then a Hold_All bit goes high. I think the problem I'm having is I'm thinking of it like a program, and not hardware.

When I implement it on my de1 board the hold_all bit always goes high after 32 clks no matter what my N value is. I tried changing the bit width of N to see if that would have any effect, and it did. When changed to 2 the Hold_all bit goes high at 8 clks . 8 = 2^(2 +1), which is the first number N can't count to.

Thanks for the help

~Triston 


Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
----------------------------------->
Entity Compare_N is
	Generic( k :integer :=2);
	Port(
			clk,clr      :  in std_logic;
			N            :  in Unsigned(k downto 0);
			Hold_all     :  out std_logic
			
			);
End Compare_N;
---------------------------------->
Architecture Compare_inside of Compare_N is
 Signal All_hold_int : std_logic;
 
 Signal c_int        : integer range 0 to ((2**(k+1))-1);
Begin
	---------- Compare Process -------------------------->
  Compare_Me : Process(clk,clr,N)
	Variable Num_Val : integer Range 0 to ((2**(k+1))-1);
	Variable c       : integer range 0 to ((2**(k+1))-1);
  begin
    
    Num_Val := To_Integer(N);
    
    
    --****************************************************************  
    if (clr ='1') then
       c := 0;
       All_hold_int <= '0';
       
    elsif(clk'event and clk='1') then
          
          if (All_hold_int = '0') then
           c := c + 1;
          end if;
                    -------------------------------  
                    if( c = Num_Val  ) then
                      All_hold_int <= '1';
                    end if;
                    
                    -------------------------------
      
     end if;
          
          c_int <= c;
          
  End Process Compare_Me;
  ---------------------------------------------------------
 
 
 Hold_All <= All_hold_int;
 
 End Compare_inside;

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I'm not sure it would change anything for the synthesizer, but could you try to move the line

    Num_Val := To_Integer(N);
    inside the clock event part?

    I'm don't know how the synthesizer would handle your line outside of the if. It is better to stick as much as possible to the recommended structures.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    And by the way you don't really need to convert to integers. If you use unsigned, you can do additions and comparisons without casting. The only difference would be the reset assignment, that would be:

    c := (others => '0');
    or:
    c := to_unsigned(0,k);

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Are you asserting the clr signal to restart the count?

    it could also have been a function you you assigning variables outside of the clock branch.

    Try the following code instead: 

    
Architecture Compare_inside of Compare_N is
 Signal All_hold_int : std_logic;
 
 Signal c_int        : integer range 0 to ((2**(k+1))-1);
Begin
    ---------- Compare Process -------------------------->
  Compare_Me : Process(clk,clr)    
  begin
    
    --****************************************************************  
    if (clr ='1') then
       c_int        <=  0;
       All_hold_int <= '0';
       
    elsif(clk'event and clk='1') then
        
       if (All_hold_int = '0') then
           c_int <= c_int + 1;
        end if;
       -------------------------------  
       if( N = c_int  ) then
         All_hold_int <= '1';
       end if;
       
       -------------------------------
      
     end if;
  End Process Compare_Me;
  ---------------------------------------------------------
 
 
 Hold_All <= All_hold_int;
 
 End Compare_inside;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thanks for straightening me out a bit more on casting Daixiwen.

    I tried Tricky's code and now the "Hold_All" bit goes high on the first clk, regardless of N value. I'm getting 5 warnings, all which don't appear threatening except for one referring to something called LogicLock. Don't suppose this "magical" warning might be responsible for my synthesis issue?

    I could try to play with the code structure some more to get it to synthesize properly, but I'm starting to think that the best way to get around this hurdle might be to design this counter with small logical blocks, to ensure that the synthesizer has less opportunity to make an assumption, or optimization that causes the design to not function as intended. Would either of you recommend this route?

    Tricky, I am asserting the clr signal to ensure that I can put the counter in a known state (e.g. c_int = 0, not 2).

    Thanks again for the assist.

    *************************** Update *************************************

    I just tried making everything an unsigned and dropping the cast, and now the problem that I originally had is back.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    That's really odd...

    Could you use signaltap and record all the signals, to see what is happening?