Problems with Synthesis ?

Thanks for straightening me out a bit more on casting Daixiwen.

I tried Tricky's code and now the "Hold_All" bit goes high on the first clk, regardless of N value. I'm getting 5 warnings, all which don't appear threatening except for one referring to something called LogicLock. Don't suppose this "magical" warning might be responsible for my synthesis issue?

I could try to play with the code structure some more to get it to synthesize properly, but I'm starting to think that the best way to get around this hurdle might be to design this counter with small logical blocks, to ensure that the synthesizer has less opportunity to make an assumption, or optimization that causes the design to not function as intended. Would either of you recommend this route?

Tricky, I am asserting the clr signal to ensure that I can put the counter in a known state (e.g. c_int = 0, not 2).

Thanks again for the assist.

*************************** Update *************************************

I just tried making everything an unsigned and dropping the cast, and now the problem that I originally had is back.