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Altera_Forum
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17 years ago

Problems with lvds

Hi,all I'm working with an ADC with lvds interface,using ep1s25f780c5. For there aren't available differental clk-input pins so I use a gpio instead. It runs @200MHz,400Mbps and works well. B...
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Altera_Forum
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17 years ago

The clock phase may need a correction. Using regular Stratix SERDES and clock PLL, the phase adjustment is easy. But dedicated clock inputs are required to clock the PLL.