Problems with lvds

Hi,all

I'm working with an ADC with lvds interface,using ep1s25f780c5.

For there aren't available differental clk-input pins so I use a gpio instead. It runs @200MHz,400Mbps and works well.

But recently I found that there are some wrong data. for all data should larger than 128(8bits) but some of them is lower than 50. It seems that sth is wrong with the lvds decoder.The error rate is about 1.5%

Anyone have some idears?

For I use a altlvds IPCore whithout regular clk input so I wrote a module to generate the decoding function,the code:

module MYLVDS(

iDCO,

iFCO,

iADDATA,

oADDATA,

oDVAL

);

input iDCO;

input iFCO;

input[3:0] iADDATA;

output reg[31:0] oADDATA;

output reg oDVAL;

reg[1:0] LastFCO;

reg[15:0] tDATA0,tDATA1,tDATA2,tDATA3;

wire[7:0] rx_out;

wire[1:0] rx_out_fco;

always@(posedge iDCO)begin

tDATA0[15:0]<={tDATA0[13:0],rx_out[1:0]};

tDATA1[15:0]<={tDATA1[13:0],rx_out[3:2]};

tDATA2[15:0]<={tDATA2[13:0],rx_out[5:4]};

tDATA3[15:0]<={tDATA3[13:0],rx_out[7:6]};

end

always@(posedge iDCO)

LastFCO<=rx_out_fco;

always@(posedge iDCO)

if((LastFCO==2'b0)&&(rx_out_fco!=2'b0)) //posedge of iFCO

begin

oADDATA[7:0]<=tDATA0[7:0];

oADDATA[15:8]<=tDATA1[7:0];

oADDATA[23:16]<=tDATA2[7:0];

oADDATA[31:24]<=tDATA3[7:0];

end

else

oADDATA<=oADDATA;

always@(posedge iDCO)

oDVAL<=~rx_out_fco[0];

altlvds u0 (

.rx_in({iADDATA[3:0],iFCO}),

.rx_inclock(iDCO),

.rx_out({rx_out[7:0],rx_out_fco[1:0]})

);

endmodule