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Altera_Forum
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14 years ago

problems with inputs vs. constants

Hi all, I am having problems using Input ports to control a function in VHDL. I think it may be a synthesis problem, but I am not sure. I could just not be understanding something or doing som...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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Are you referring to the process: ROISELECT?

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Yes. UPDATE can cause timing violations if it's asynchronous to CLK. Other than said in my previous post, RENA can't, because it's sampled by UPDATE.