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Honored Contributor
Honored Contributorproblems with inputs vs. constants
Hi all, I am having problems using Input ports to control a function in VHDL. I think it may be a synthesis problem, but I am not sure. I could just not be understanding something or doing som...
Altera_ForumHonored Contributor
Honored ContributorSorry, I know the code isn't very readable:oops:. Are you referring to the process: ROISELECT?
