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Altera_Forum
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14 years ago

problems with inputs vs. constants

Hi all, I am having problems using Input ports to control a function in VHDL. I think it may be a synthesis problem, but I am not sure. I could just not be understanding something or doing som...
Altera_Forum's avatar
Altera_Forum
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14 years ago

When it comes to inputs, compilers make two types of response.

If your input is a constant then it reduces logic to the case of constant value only. If your input is not constant then it has to cater for all possibilities. This is possible in the sense of logic decisions but compilers do not support synthesizing different circuits per input value. For example in the case of 16 bits then it will need to create 2^16 circuits !!

Thus for a given build, the compiler needs to settle with one case of build.

the reverse is also true. If you have a variable input and decided to fix it as constant for testing stage then the compiler will remove a lot of logic that will be needed at sign off and may cause trouble to you with your manager at the end.