problems with clock !!

Hi, I can't see the clock on the oscilloscope, i need this test to see if it works, then i'll use it for Nios.

I test the clock_50 with this code:

entity provaClock is

port(CLOCK_50: in std_logic;

uscita :out std_logic

);

end entity provaClock;

architecture ar of provaClock is

signal coll :std_logic;

begin

coll<=CLOCK_50;

uscita<=coll;

end ar;

FPGA Cyclone ii

PIN Assignment

uscita --- PIN_K20

CLOCK_50 -- PIN_B12

Software Quartus 9.1 Web Edition

why ?????

Thanks