problems on my thesis

As Tricky mentions, making your own clock (divider) is not good design practice. That aside, this is not the major problem in your design.

You have used signals that are not connected to pins of your DE0 board.

I added external pins BUTTON and CLOCK_50 instead of your reset and clk_default.

Also the vectors Hcount and Vcount were too small: 4 bit vectors to represent horizontal position from 0-800 as well as vertical position 0-524.

With the adapted code below it runs on my DE0.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vga is
 port (
--  reset : in std_logic;
--  clk_default : in std_logic; --default is 50 MHz 
      BUTTON : in std_logic_vector (2 downto 0);    -- Sanmao
  CLOCK_50 : in std_logic;                      -- Sanmao
--  VGA_CLK, --Dot clock to DAC
--  VGA_BLANK, --Active-Low DAC blanking control
--  VGA_SYNC, --Active-Low DAC Sync on Green
  VGA_HS, --Active-Low Horizontal Sync
  VGA_VS : out std_logic; --Active-Low Vertical Sync
  VGA_R, VGA_G, VGA_B : out std_logic_vector(3 downto 0)
 );
end vga;
architecture rtl of vga is
--Video parameters
 constant HTOTAL : integer := 800;
 constant HSYNC : integer := 96;
 constant HBACK_PORCH : integer := 48;
 constant HACTIVE : integer := 640;
 constant HFRONT_PORCH : integer := 16;
 constant VTOTAL : integer := 525;
 constant VSYNC : integer := 2;
 constant VBACK_PORCH : integer := 33;
 constant VACTIVE : integer := 480;
 constant VFRONT_PORCH : integer := 10;
 constant RECTANGLE_HSTART : integer := 100;
 constant RECTANGLE_HEND : integer := 540;
 constant RECTANGLE_VSTART : integer := 100;
 constant RECTANGLE_VEND : integer := 380;
--Horizontal position (0-800)
 signal Hcount : std_logic_vector(9 downto 0);  -- Sanmao
--Vertical position (0-524)
 signal Vcount : std_logic_vector(9 downto 0);  -- Sanmao
 signal EndOfLine, EndOfField : std_logic;
 signal vga_hblank, vga_hsync,vga_vblank, vga_vsync : std_logic; --Sync. signals
 signal rectangle_h, rectangle_v, rectangle : std_logic; --rectangle area
 signal clk : std_logic; --Should be 25.125 MHz
 signal clk_default : std_logic;
 signal reset : std_logic;
begin
 
 CDivider : process (clk_default)
  begin 
    if clk_default'event and clk_default = '1' then
      if (clk = '0') then
        clk <= '1';
      else
        clk <= '0';
      end if;
    end if;
  end process CDivider;
 
 HCounter : process (clk, reset)
 begin
  if reset = '1' then
   Hcount <= (others => '0');
  elsif clk'event and clk = '1' then
   if EndOfLine = '1' then
    Hcount <= (others => '0');
   else
    Hcount <= Hcount + 1;
   end if;
  end if;
 end process HCounter;
 EndOfLine <= '1' when Hcount = HTOTAL - 1 else '0';
 VCounter: process (clk, reset)
 begin
  if reset = '1' then
   Vcount <= (others => '0');
  elsif clk'event and clk = '1' then
   if EndOfLine = '1' then
    if EndOfField = '1' then
     Vcount <= (others => '0');
    else
     Vcount <= Vcount + 1;
    end if;
   end if;
  end if;
 end process VCounter;
 
 EndOfField <= '1' when Vcount = VTOTAL - 1 else '0';
 
 HSyncGen : process (clk, reset)
 begin
  if reset = '1' then
   vga_hsync <= '1';
  elsif clk'event and clk = '1' then
   if EndOfLine = '1' then
    vga_hsync <= '1';
   elsif Hcount = HSYNC - 1 then
    vga_hsync <= '0';
   end if;
  end if;
 end process HSyncGen;
 
 HBlankGen : process (clk, reset)
 begin
  if reset = '1' then
   vga_hblank <= '1';
  elsif clk'event and clk = '1' then
   if Hcount = HSYNC + HBACK_PORCH then
    vga_hblank <= '0';
   elsif Hcount = HSYNC + HBACK_PORCH + HACTIVE then
    vga_hblank <= '1';
   end if;
  end if;
 end process HBlankGen;
 
 VSyncGen : process (clk, reset)
 begin
  if reset = '1' then
   vga_vsync <= '1';
  elsif clk'event and clk = '1' then
   if EndOfLine ='1' then
    if EndOfField = '1' then
     vga_vsync <= '1';
    elsif Vcount = VSYNC - 1 then
     vga_vsync <= '0';
    end if;
   end if;
  end if;
 end process VSyncGen;
 
 VBlankGen : process (clk, reset)
 begin
  if reset = '1' then
   vga_vblank <= '1';
  elsif clk'event and clk = '1' then
   if EndOfLine = '1' then
    if Vcount = VSYNC + VBACK_PORCH - 1 then
     vga_vblank <= '0';
    elsif Vcount = VSYNC + VBACK_PORCH + VACTIVE - 1 then
     vga_vblank <= '1';
    end if;
   end if;
  end if;
 end process VBlankGen;
 
 RectangleHGen : process (clk, reset)
 begin
  if reset = '1' then
   rectangle_h <= '1';
  elsif clk'event and clk = '1' then
   if Hcount = HSYNC + HBACK_PORCH + RECTANGLE_HSTART then
    rectangle_h <= '1';
   elsif Hcount = HSYNC + HBACK_PORCH + RECTANGLE_HEND then
    rectangle_h <= '0';
   end if;
  end if;
 end process RectangleHGen;
 RectangleVGen : process (clk, reset)
 begin
  if reset = '1' then
   rectangle_v <= '0';
  elsif clk'event and clk = '1' then
   if EndOfLine = '1' then
    if Vcount = VSYNC + VBACK_PORCH - 1 + RECTANGLE_VSTART then
     rectangle_v <= '1';
    elsif Vcount = VSYNC + VBACK_PORCH - 1 + RECTANGLE_VEND then
     rectangle_v <= '0';
    end if;
   end if;
  end if;
 end process RectangleVGen;
 rectangle <= rectangle_h and rectangle_v;
 
 VideoOut: process (clk, reset)
 begin
 if reset = '1' then
  VGA_R <= "0000";
  VGA_G <= "0000";
  VGA_B <= "0000";
 elsif clk'event and clk = '1' then
  if rectangle = '1' then
   VGA_R <= "1111";
   VGA_G <= "1111";
   VGA_B <= "1111";
  elsif vga_hblank = '0' and vga_vblank ='0' then
   VGA_R <= "0000";
   VGA_G <= "0000";
   VGA_B <= "1111";
  else
   VGA_R <= "0000";
   VGA_G <= "0000";
   VGA_B <= "0000";
  end if;
 end if;
 end process VideoOut;
-- VGA_CLK <= clk;
 VGA_HS <= not vga_hsync;
 VGA_VS <= not vga_vsync;
 clk_default <= CLOCK_50;  -- Sanmao
 reset <= not BUTTON(0);   -- Sanmao
-- VGA_SYNC <= '0';
-- VGA_BLANK <= not (vga_hsync or vga_vsync);
end rtl;

Good luck with Tetris!