problems about EPCS devices' storage format

You need a SPI interface at your CPU (hard- or software) and you need to tri-state the FPGA lines driving the EPCS during CPU access by pulling nCE high. That's the hardware side.

For the software side, you write the *.rbf content to the SPI flash starting at sector 0. As said, the bit order has to be reversed compared to the usual SPI format.

In addition, there's an Altera srunner project with source code for EPCS programming. As another hint, if you have doubts about data bit order, "file formats" and such, you can also read back a correctly programmed EPCS device from your CPU and compare to the original configuration files. I take for granted, that you have at least an operational JTAG interface in your target hardware, so every information is at your fingertips.