problem

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter_devidor is
port (
     CLK, RST :in std_logic;
     devided_clk : inout std_logic
--   Q :out std_logic_vector(24 downto 0)
) ;
end counter_devidor;
architecture beh of counter_devidor is
signal QL : std_logic_vector (24 downto 0);
begin
process(CLK, RST) begin
  if (RST = '1') then
    QL <= "1011111010111100001000000";        
    devided_clk <= '0';
  elsif (CLK'event and CLK = '1') then
    if (QL = "0000000000000000000000000") then       
      QL <= "1011111010111100001000000";         
      devided_clk <= not(devided_clk);            
    else
      QL <= QL - 1; 
                          
    end if;
  end if;
end process;
--Q <= QL;
end beh;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter60seconds  is 
port  (
clk, reset: in std_logic; 
seconds60 : inout   std_logic  
);
end counter60seconds; 
architecture beh of counter60seconds is  
signal cnt : std_logic_vector (5 downto 0);
--signal  sec_sign : std_logic; 
begin
process   (clk, reset ) 
begin 
  if (reset = '1') then  cnt <= "111100" ; seconds60 <= '0' ;  else  
   if (clk'event and clk = '1') then
   if (reset /= '1') then if (cnt = "000001") then seconds60 <= not(seconds60);   cnt <= "011110";   else  cnt <= cnt - 1 ; end if;  end if ;  
    end if;                                                                                                                       
end if ; 
end process; 
end beh; 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter_10_min is
port (
     CLK, RST :in std_logic;
     devided_clk_10_sec : inout std_logic; 
     Q_10_min :out std_logic_vector(3 downto 0);
     numbers_min10 :inout std_logic_vector(3 downto 0);
     flagFirst : inout std_logic
) ;
end counter_10_min;
architecture beh of counter_10_min is
signal QL : std_logic_vector (3 downto 0);
--signal  numbers_sec10_sign  :  std_logic_vector (3 downto 0);
begin
process(CLK, RST) begin
  if (RST = '1') then
    QL <= "1010";       
    flagFirst <= '0';
  --  numbers_sec10 <= "0000";
   devided_clk_10_sec <= '0';
  elsif (CLK'event and CLK = '1') then
    if (QL = "0001") then       
      QL <= "0101";         
      devided_clk_10_sec <= not(devided_clk_10_sec);
       flagFirst <= '1';       
    else
   
      QL <= QL - 1; 
      
                          
    end if;
  end if;
end process;
--process(CLK, RST, devided_clk_10_sec) begin
  --  if (RST = '1') then
    -- numbers_sec10_sign <= "0000"; 
  --elsif (devided_clk_10_sec'event and devided_clk_10_sec='1' ) then 
  --numbers_sec10 <= "0000"; 
  --numbers_sec10_sign <= numbers_sec10_sign +1 ; 
  --end if ; 
 -- end if ; 
 -- end process;
  
Q_10_min <= QL;
--numbers_sec10 <=  numbers_sec10_sign;
end beh;

use ieee.std_logic_1164.all ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counterSixtyMin is 
port  (
clk_in_10_min, reset: in std_logic; 
q_Sixty_min_7_segment : out   std_logic_vector (3 downto 0)  ;
--q_Sixty_min : out   std_logic_vector (2 downto 0)  ;
q_Sixty_min_Signal : out std_logic;
rst : in std_logic
);
end counterSixtyMin; 
architecture arch of counterSixtyMin is  
signal cnt : std_logic_vector (2 downto 0);
signal cnt_7_segnent : std_logic_vector (3 downto 0);
begin
process   (clk_in_10_min, reset , rst ) 
begin 
if (reset = '1' or rst = '1') then  cnt <= "000"  ;   cnt_7_segnent <= "0000";
  elsif (clk_in_10_min'event and clk_in_10_min = '0') then
  
  if (cnt = "101")  then cnt <= "000" ;   cnt_7_segnent <= "0000"; else cnt <= cnt +1 ; cnt_7_segnent <= cnt_7_segnent+ 1; end if ;
  
  end if ; 
  
end process; 
--q_Sixty_min <= cnt; 
q_Sixty_min_Signal <=  cnt(2);
q_Sixty_min_7_segment <= cnt_7_segnent ;
end arch; 

library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counterTenHours is 
port  (
clk_1_hour , reset: in std_logic; 
q_10_HOURS : out   std_logic_vector (3 downto 0)  ;
q_10_hoursSignal : out std_logic;
rst : in std_logic
);
end counterTenHours; 
architecture arch of counterTenHours is  
signal cnt : std_logic_vector (3 downto 0);
begin
process   (clk_1_hour, reset , rst) 
begin 
if (reset = '1' or rst = '1') then  cnt <= "0000" ;     
  elsif (clk_1_hour'event and clk_1_hour = '0') then
  
  if (cnt = "1001")  then cnt <= "0000" ; else cnt <= cnt +1 ; end if ;
  
  end if ; 
  
end process; 
q_10_HOURS <= cnt; 
q_10_hoursSignal <=  cnt(3);
end arch;