problem with writing testbench

hi

I installed a qurtusii web edition included a modelsim 6.5

i've written a counter code in verilog and a simple testbench also.

when i compile the code in quartus there is no error but in modelsim when inputs change there is no change in output.

thank you

this is the code.

module counter4bit (

input clk,

input enable,

input reset,

output reg [3:0] outbits

);

reg [3:0] counter ;

always @ (posedge clk)

begin

if(enable == 1)

begin

if(reset == 1)

begin

counter <= 4'b0000;

end

else

begin

counter <= counter +1 ;

outbits <= counter ;

end

end

else

begin

outbits = counter ;

end

end

endmodule

module count_t () ;

reg resett, enablet,clkt ;

wire [3:0] out ;

counter4bit c1(

clkt,

enablet,

resett,

out

);

initial

begin

resett = 0 ;

clkt = 1 ;

enablet = 0 ;

# 10 enablet = 1 ;

end

always

# 20 clkt = ~clkt ;

endmodule