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Honored Contributor
Honored Contributorproblem with writing testbench
hi I installed a qurtusii web edition included a modelsim 6.5 i've written a counter code in verilog and a simple testbench also. when i compile the code in quartus there is no error but in m...
Altera_ForumHonored Contributor
Honored ContributorYou are not resetting your counter to zero, which you must, because modelsim will start with counter set to 'UUUU'.
Also, note that in your module, the reset is synchronous and subject to the enable signal. Thus, you need to have enable = 1 and reset = 1 long enough for count to reset to zero.
