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Altera_Forum
Honored Contributor
17 years agoProblem with "WHILE...loop"
Hello, I am trying to write an FSM module using VHDL.I have to make a "while...loop" that doesn't concern all the states but only a pre-determined number of them.Here is the FSM diagram schematic...
Altera_Forum
Honored Contributor
17 years agoThe synthesis for the "while" loops is rather complicated as the amount of terms the loop will be taken is not known at compile time. This would mean that separate hardware would be generated for every individual value of the signals to be tested in your while loop.
So the code:while (n <= 15) loop would have to be expanded in hardware for every individual case where n = 0, n = 1, n = 2 ... n = 15. I have the impression that there are a number of states in which you would like to stay for a number of turns (indicated by the end conditions of your while expression). In the case that your state transitions (also the loops from a state to itself) are taking place synchronized by the clock, you can implement the statemachine by using "if" expressions instead of the "while" loops. In the "if" expression as long as the end condition is not met, your etat_suivant next state should remain the same as the previous value. Only when the end condition is met, you should update the next state etat_suivant.