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Altera_Forum's avatar
Altera_Forum
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17 years ago

Problem with "WHILE...loop"

Hello, I am trying to write an FSM module using VHDL.I have to make a "while...loop" that doesn't concern all the states but only a pre-determined number of them.Here is the FSM diagram schematic...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Actually there is no problem with the clock since it is written in a separate process: 


process(reset,BCLK)
        begin
        if reset = '1' then 
        adr_reg <= adr_reg_1E;
        val_reg_byte_1 <= val_reg_1E(8 downto 1);
        val_reg_byte_2<= "00000000";
        
        elsif (BCLK'event and BCLK = '1') then 
        etat_courant <= etat_suivant;
        end if;
        end process;

I am very sure the problem lies in the loop.Please take a look at the FSM schematic.