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Honored Contributor
Honored ContributorProblem with "WHILE...loop"
Hello, I am trying to write an FSM module using VHDL.I have to make a "while...loop" that doesn't concern all the states but only a pre-determined number of them.Here is the FSM diagram schematic...
Altera_ForumHonored Contributor
Honored ContributorI do not see any place where your VHDL code is synchronized by a clock event.
For such a finite state-machine you should define a synchronous system clocked with an external clock.
