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Altera_Forum
Honored Contributor
18 years agoProblem with WHILE Loop
I am currently trying to compile and simulate a vhdl ROM file. I am having problem with the while loop, which is used to read the ROM. The following is the vhdl-code: entity mc8051_rom is ...
Altera_Forum
Honored Contributor
18 years agoYou're going to be using the Quartus simulator, in which you draw a waveform as the input. (You can have it auto-count, which might be all you need). But your testbench would actually get synthesized into hardware, whether you want it to or not. Modelsim(or other 3rd party simulators) are for simulating testbenches.