Problem with WHILE Loop

i want to simulate it. but before simulating it in Quartus II, i must compile it first, right?

because of that error, the compilation could not be completed.

i tried to solve the problem by creating 8 while-loops with each loop consists of iteration less than 10000. The following is the vhdl-codes:

if (not s_init) then

v_loop := 0;

while (v_loop < 8000) loop

readline(f_initfile,v_line);

read(v_line,v_rom_data(v_loop));

v_loop := v_loop + 1;

end loop;

v_loop := 8000;

while (v_loop < 16000 ) loop

readline(f_initfile,v_line);

read(v_line,v_rom_data(v_loop));

v_loop := v_loop + 1;

end loop;

v_loop := 16000;

while (v_loop < 24000 ) loop

readline(f_initfile,v_line);

read(v_line,v_rom_data(v_loop));

v_loop := v_loop + 1;

end loop;

v_loop := 24000;

while (v_loop < 32000 ) loop

readline(f_initfile,v_line);

read(v_line,v_rom_data(v_loop));

v_loop := v_loop + 1;

end loop;

v_loop := 32000;

while (v_loop < 40000 ) loop

readline(f_initfile,v_line);

read(v_line,v_rom_data(v_loop));

v_loop := v_loop + 1;

end loop;

v_loop := 40000;

while (v_loop < 48000 ) loop

readline(f_initfile,v_line);

read(v_line,v_rom_data(v_loop));

v_loop := v_loop + 1;

end loop;

v_loop := 48000;

while (v_loop < 56000 ) loop

readline(f_initfile,v_line);

read(v_line,v_rom_data(v_loop));

v_loop := v_loop + 1;

end loop;

v_loop := 56000;

while (v_loop < 64000 ) loop

readline(f_initfile,v_line);

read(v_line,v_rom_data(v_loop));

v_loop := v_loop + 1;

end loop;

v_loop := 64000;

while ((not endfile(f_initfile) and (v_loop < 65535)) loop

readline(f_initfile,v_line);

read(v_line,v_rom_data(v_loop));

v_loop := v_loop + 1;

end loop;

s_init <= true;

end if;

but then i got the error statement:

"error: vhdl error at mc8051_rom.vhd(153): index value 65536 is outside the range (65535 downto 0) of object "v_rom_data""

what should i do next?