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Altera_Forum
Honored Contributor
18 years agoProblem with WHILE Loop
I am currently trying to compile and simulate a vhdl ROM file. I am having problem with the while loop, which is used to read the ROM. The following is the vhdl-code: entity mc8051_rom is ...
Altera_Forum
Honored Contributor
18 years agoI think the message is straightforward, that a loop must terminate before 10,000, while you have 65,536.
Where is this error coming from, Quartus? Is this code supposed to simulate or synthesize? If it's for simulation, then it would run in Modelsim. If you wanted to synthesize this, my guess is that this doesn't synthesize to a counter. (The endfile command looks like a simulation construct, unless you have some hardware for this?) If you really want to synthesize a counter for reading, then make a signal that is the correct number of bits and just have it increment on each clock.