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Altera_Forum
Honored Contributor
Honored ContributorProblem with verilog
First of all excuse my english (french guy) Well i want to do something simple with quartus but it doesn't work! the idea is the following one: i have a counter "count", 2 clocks "...
Altera_ForumHonored Contributor
Honored ContributorAnother method would be to use two counters for each clock domain. Then design a module to re sync the counter values to the same clock domain before adding them together to get the total count.
