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Altera_Forum's avatar
Altera_Forum
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16 years ago

Problem with verilog

First of all excuse my english (french guy) Well i want to do something simple with quartus but it doesn't work! the idea is the following one: i have a counter "count", 2 clocks "...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Typically it's not possible to use two clocks on a register.

You should solve it like this:

always(clk) begin

if (bu==0) begin

count <= count + 1'd1;

end else begin

count <= count + 5'd20;

end

end